----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:52:24 04/07/2008 
-- Design Name: 
-- Module Name:    CameraMapper - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CameraMapper is
    Port ( CamPixelFlags : in  STD_LOGIC_VECTOR (1 downto 0);
				CamPixelPair : in std_logic_vector(15 downto 0);
           CamPixAdr : out  STD_LOGIC_VECTOR (17 downto 0);
           CamPixWrite : in  STD_LOGIC;
			  wen_out : out  STD_LOGIC;
           clk : in  STD_LOGIC);
end CameraMapper;

architecture Behavioral of CameraMapper is


	signal origin : std_logic_vector(17 downto 0) := (others=>'0');
	signal row_address : std_logic_vector(17 downto 0);
	signal word_ctr : std_logic_vector(17 downto 0);
	signal line_ctr : std_logic_vector(9 downto 0);
	signal Vstart, Hstart : std_logic;

begin

	Vstart <= CamPixelFlags(1);
	Hstart <= CamPixelFlags(0);
	
	CamPixAdr <= row_address+word_ctr;
	
	mapaddr : process(clk)
	begin
--		if rising_edge(clk) then
--
--			wen_out <= '0';
--		
--			if CamPixWrite = '1' then
--				--if (Hstart = '1') and (Vstart = '1') then
--				if CamPixelPair = x"0000" then
--					row_address <= origin;
--					word_ctr <= (others=>'0');
--				elsif Hstart = '1' then
--					row_address <= row_address+320; -- two bytes per word
--					word_ctr <= (others=>'0');
--				else
--					word_ctr <= word_ctr+1;
--				end if;
--				wen_out <='1';
--			end if;
--			
--		end if;

		if rising_edge(clk) then
			wen_out <= '0';
			if CamPixWrite = '1' then
				word_ctr <= word_ctr+1;
				wen_out <= '1';
				if word_ctr = 16 then
					word_ctr<=(others=>'0');
					row_address<= row_address+320;
					line_ctr<=line_ctr+1;
				end if;
				if line_ctr = 450 then
					line_ctr <= (others=>'0');
					row_address <= origin;
				end if;
			end if;
		end if;

	end process;

end Behavioral;

